{"id":1342,"date":"2013-05-28T09:38:00","date_gmt":"2013-05-28T01:38:00","guid":{"rendered":"http:\/\/nazrulanuar.wordpress.com\/?page_id=1342"},"modified":"2023-11-20T15:15:10","modified_gmt":"2023-11-20T07:15:10","slug":"adiabatic-research-materials","status":"publish","type":"page","link":"https:\/\/www.nazrulanuar.com\/author\/adiabatic-research-materials\/","title":{"rendered":"Adiabatic Circuit Research"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"1342\" class=\"elementor elementor-1342\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-7335 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"7335\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-357f\" data-id=\"357f\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-3bb2 elementor-widget elementor-widget-text-editor\" data-id=\"3bb2\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>My DPhil. work. Feel free to download and refer.<\/p><ul><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/zemi.pdf\">2008.09.26 Adiabatic logic simulation &amp; energy dissipation comparison<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/zemi12.pdf\">2008.10.03 Adiabatic logic simulation &amp; energy dissipation at different load capacitance<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/zemi2.pdf\">2008.10.10 Circuits simulation with new diagrams<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi31.pdf\">2008.10.17 Adiabatic circuits simulations and energy dissipation comparison<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi41.pdf\">2008.10.24 Low power adiabatic logic circuit simulations<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/report1.pdf\">2008.10.31 Draft for young researchers and graduate student workshop<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/lsi-fundamental-master-course.pdf\">2008.11.14 LSI fundamental master course<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/zemi411.pdf\">2008.11.21 (my birthday) Adiabatic circuits simulation and new proposed circuit<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/zemi5.pdf\">2008.12.19 New proposed adiabatic logic inverters<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/sotai2009_1.pdf\">2008.12.25 Paper for IEICE Ehime Univ. (Mar 2009)<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi_main11.pdf\">2009.01.08\u00a02PASCL : Energy dissipation at various input\u00a0&amp; pulse driving voltage<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi_main3.pdf\">2009.01.16 2PASCL : Energy dissipation of NAND circuit and simulation with trapezoidal and sine voltage clocking power<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/01\/zemi_main4.pdf\">2009.01.23 2PASCL: Energy dissipation of NAND circuit using trapezoidal and split level pulse driving and the effects of rise and fall time<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi_main6.pdf\">2009.01.29 2PASCL: Energy dissipation of NAND circuit using new split level driving value and CMOS bulk connection<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi_main7.pdf\">2009.02.06 2PASCL: Energy dissipation of NOR and exclusive-OR gate circuit using sinusoidal split level driving voltage<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi_main8.pdf\">2009.02.27 Energy dissipation comparison: 2PASCL versus CMOS for 2 multiplexer (2:1MUX) and 1-bit full adder (FA)<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2013\/05\/zemi_main9.pdf\">2009.03.06 1-bit full adder (FA) with new exclusive-OR of 2PASCL and introduction to 2PASCL Ripple Carry Adder (RCA)<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/03\/zemi_main11.pdf\">2009.03.27 4-bit Ripple Carry Adder (RCA) of 2PASCL: comparison with static CMOS<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/authorwp-content\/uploads\/2009\/04\/zemi_main12.pdf\">2009.04.03 Supply clock generator (driver) circuit for 2PASCL<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/04\/zemi_main141.pdf\">2009.04.10 Supply clock generation (driver) circuit for 2PASCL : Hara active inductor equivalent circuit and simulation<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/05\/zemi_main15.pdf\">2009.04.17 Supply clock (driver) circuit for 2PASCL: nMOS circuit characteristic prior to Hara active inductor simulation<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/05\/zemi_main16.pdf\">2009.05.15 Voltage driver and clock circuit for 2PASCL<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/08\/zemi_main18.pdf\">2009.05.22 40 MHz LC Voltage driver and clock circuit for 2PASCL<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/08\/zemi_main191.pdf\">2009.06.05 40 MHz LC Voltage driver and clock circuit for 2PASCL<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/08\/zemi_main1101.pdf\">2009.06.19 SR and Clocked D Flip-flops Using 2PASCL :<\/a><\/li><li><a href=\"http:\/\/www.nazrulanuar.com\/author\/wp-content\/uploads\/2009\/11\/zemi_main1112.pdf\">2009.10.23 2PASCL &#8211; Power clocks evaluation and unsymmetrical evaluation<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main113.pdf\">2009.11.09 Chain inverter and NAND logic camparison of 2PASCL and 2PADCL<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main114.pdf\">2009.11.13 A comparison of NOT, NAND and NOR of 2PASCL and 2PADCL<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main115.pdf\">2009.11.20 Overlapped power voltage and low Vdd evaluation<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main116.pdf\">2009.12.25 Preliminary study on 4&#215;4 array multiplier and plans for 2010<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main117.pdf\">2010.01.08 SPICE simulation on 2PASCL 4&#215;4 bit array multiplier<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main118.pdf\">2010.01.15 4&#215;4 bit array 2PASCL multiplier simulation : a power dissipation comparison with CMOS<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main119.pdf\">2010.01.22 4&#215;4 bit array 2PASCL multiplier simulation : a power dissipation comparison and lay-out design<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main120.pdf\">2010.02.07 4&#215;4 bit array 2PASCL multiplier simulation and lay-out design<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main121.pdf\">2010.02.12 Simulation on logic gates using 1.2um standard CMOS process<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main122.pdf\">2010.02.19 2PASCL: Simulation on logic gates using 1.2$mu$m standard CMOS process<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main123.pdf\">2010.02.26 4&#215;4-bit 2PASCL Multiplier Simulation using 1.2um process : evaluation on high ripples at outputs<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main124.pdf\">2010.03.05 4&#215;4-bit 2PASCL Multiplier Simulation using 1.2um process : evaluation on half adders<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main125.pdf\">2010.04.09 Electrical current evaluation of 2PASCL and CMOS<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main126.pdf\">2010.04.23 Electrical current evaluation of 2PASCL and CMOS (cont)<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main127.pdf\">2010.05.07 Evaluation on electrical current and energy dissipation at every transistor of 2PASCL\/CMOS and MOSFET diode characteristic study<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main128.pdf\">2010.05.14 Evaluation on MOSFET diodes, the need of diode in 2PASCL and doctoral thesis contents<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main129.pdf\">2010.05.28 Current characteristic study<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main131.pdf\">2010.06.24 RC circuit operation and power dissipation analysis<\/a><\/li><li><a href=\"http:\/\/nazrulanuar.files.wordpress.com\/2009\/01\/zemi_main132.pdf\">2010.12.20 RC circuit operation and power dissipation analysis<\/a><\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-ad7b30a elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"ad7b30a\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-e0197fc\" data-id=\"e0197fc\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap\">\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>My DPhil. work. Feel free to download and refer. 2008.09.26 Adiabatic logic simulation &amp; energy dissipation comparison 2008.10.03 Adiabatic logic simulation &amp; energy dissipation at different load capacitance 2008.10.10 Circuits simulation with new diagrams 2008.10.17 Adiabatic circuits simulations and energy dissipation comparison 2008.10.24 Low power adiabatic logic circuit simulations 2008.10.31 Draft for young researchers and graduate student workshop 2008.11.14 LSI &hellip; <\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"open","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1342","page","type-page","status-publish","hentry","latest_post"],"_links":{"self":[{"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/pages\/1342","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/comments?post=1342"}],"version-history":[{"count":66,"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/pages\/1342\/revisions"}],"predecessor-version":[{"id":8413,"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/pages\/1342\/revisions\/8413"}],"wp:attachment":[{"href":"https:\/\/www.nazrulanuar.com\/author\/wp-json\/wp\/v2\/media?parent=1342"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}