My DPhil. work. Feel free to download and refer.

• 2008.09.26 Adiabatic logic simulation & energy dissipation comparison
• 2008.10.03 Adiabatic logic simulation & energy dissipation at different load capacitance
• 2008.10.10 Circuits simulation with new diagrams
• 2008.10.17 Adiabatic circuits simulations and energy dissipation comparison
• 2008.10.24 Low power adiabatic logic circuit simulations
• 2008.10.31 Draft for young researchers and graduate student workshop
• 2008.11.14 LSI fundamental master course
• 2008.11.21 (my birthday) Adiabatic circuits simulation and new proposed circuit
• 2008.12.19 New proposed adiabatic logic inverters
• 2008.12.25 Paper for IEICE Ehime Univ. (Mar 2009)
• 2009.01.08 2PASCL : Energy dissipation at various input & pulse driving voltage
• 2009.01.16 2PASCL : Energy dissipation of NAND circuit and simulation with trapezoidal and sine voltage clocking power
• 2009.01.23 2PASCL: Energy dissipation of NAND circuit using trapezoidal and split level pulse driving and the effects of rise and fall time
• 2009.01.29 2PASCL: Energy dissipation of NAND circuit using new split level driving value and CMOS bulk connection
• 2009.02.06 2PASCL: Energy dissipation of NOR and exclusive-OR gate circuit using sinusoidal split level driving voltage
• 2009.02.27 Energy dissipation comparison: 2PASCL versus CMOS for 2 multiplexer (2:1MUX) and 1-bit full adder (FA)
• 2009.03.06 1-bit full adder (FA) with new exclusive-OR of 2PASCL and introduction to 2PASCL Ripple Carry Adder (RCA)
• 2009.03.27 4-bit Ripple Carry Adder (RCA) of 2PASCL: comparison with static CMOS
• 2009.04.03 Supply clock generator (driver) circuit for 2PASCL
• 2009.04.10 Supply clock generation (driver) circuit for 2PASCL : Hara active inductor equivalent circuit and simulation
• 2009.04.17 Supply clock (driver) circuit for 2PASCL: nMOS circuit characteristic prior to Hara active inductor simulation
• 2009.05.15 Voltage driver and clock circuit for 2PASCL
• 2009.05.22 40 MHz LC Voltage driver and clock circuit for 2PASCL
• 2009.06.05 40 MHz LC Voltage driver and clock circuit for 2PASCL
• 2009.06.19 SR and Clocked D Flip-flops Using 2PASCL :
• 2009.10.23 2PASCL – Power clocks evaluation and unsymmetrical evaluation
• 2009.11.09 Chain inverter and NAND logic camparison of 2PASCL and 2PADCL
• 2009.11.13 A comparison of NOT, NAND and NOR of 2PASCL and 2PADCL
• 2009.11.20 Overlapped power voltage and low Vdd evaluation
• 2009.12.25 Preliminary study on 4×4 array multiplier and plans for 2010
• 2010.01.08 SPICE simulation on 2PASCL 4×4 bit array multiplier
• 2010.01.15 4×4 bit array 2PASCL multiplier simulation : a power dissipation comparison with CMOS
• 2010.01.22 4×4 bit array 2PASCL multiplier simulation : a power dissipation comparison and lay-out design
• 2010.02.07 4×4 bit array 2PASCL multiplier simulation and lay-out design
• 2010.02.12 Simulation on logic gates using 1.2um standard CMOS process
• 2010.02.19 2PASCL: Simulation on logic gates using 1.2$mu$m standard CMOS process
• 2010.02.26 4×4-bit 2PASCL Multiplier Simulation using 1.2um process : evaluation on high ripples at outputs
• 2010.03.05 4×4-bit 2PASCL Multiplier Simulation using 1.2um process : evaluation on half adders
• 2010.04.09 Electrical current evaluation of 2PASCL and CMOS
• 2010.04.23 Electrical current evaluation of 2PASCL and CMOS (cont)
• 2010.05.07 Evaluation on electrical current and energy dissipation at every transistor of 2PASCL/CMOS and MOSFET diode characteristic study
• 2010.05.14 Evaluation on MOSFET diodes, the need of diode in 2PASCL and doctoral thesis contents
• 2010.05.28 Current characteristic study
• 2010.06.24 RC circuit operation and power dissipation analysis
• 2010.12.20 RC circuit operation and power dissipation analysis